This invention is related generally to computer system peripheral integrated circuits and their use, and, more specifically, to a technique and circuit for enabling a master processing unit to select one of several peripheral circuits having slave processing units for data communication with the master.
A commonly used technique for transferring data between a central processing unit ("CPU") and a selected one of several peripheral circuits is by serial communication. A known serial peripheral interface ("SPI") utilizes four lines for full duplex communication, one line for digital data being received by the peripheral, another for digital data being sent by the peripheral, another for a clock signal and another for a select line. Half duplex communication requires only three lines, the line to send data from the peripheral not being utilized. All of these lines are connected between the CPU, acting as a master device, and each of the peripheral circuits, acting as slaves.
In order to avoid running separate peripheral select lines from the CPU to each of the peripheral circuits, a single line is utilized with a first data word transmitted by the CPU to each of the peripherals containing an identification of the one peripheral with which the CPU is to establish data communication. The unique identification code within each of the peripherals is then compared with that first data word, and the peripheral that detects a positive comparison enables itself for the communication while the other peripherals remain in a passive state.
This identification code comparison is usually accomplished by a slave processor that exists as part of each of the peripheral circuits executing a software routine. It is a primary object of the present invention to improve this peripheral identification technique.